ISPLSI1024-60LJ Electrically-Erasable PLD (EEPLD) - In System Programm.
From Lattice Semiconductor
| Logic Modes | CombnSeqnt |
| Military | N |
| No. of Outputs | 48 |
| Nom. Supp (V) | 5.0 |
| Number of Inputs | 54 |
| Output Config | 3-State |
| Package | QCC-J |
| Pins | 68 |
| Prod. Terms Max. | 4-7 |
| Technology | CMOS |
| t(PLH) Maximum (S) | 20n |
