5962-9062007MXA SRAM Chip Async Dual 5V 16K-bit 2K x 8 55ns 52-Pin CLLCC
From e2v Aerospace & Defense
| Access Time | 55 |
| Address Bus | 11(b) |
| Architecture | Not Required |
| Clock Freq | Not Required(MHz) |
| Density | 16384(Bit) |
| Function | MASTER |
| Mounting | Surface Mount |
| Number of I/O Lines | 8 |
| Number of Ports | 2 |
| Number of Words | 2K |
| Operating Supply Voltage (Max) | 5.5(V) |
| Operating Supply Voltage (Min) | 4.5(V) |
| Operating Supply Voltage (Typ) | 5(V) |
| Operating Temp Range | -55C to 125C |
| Operating Temperature Classification | Military |
| Package Type | CLLCC |
| Pin Count | 52 |
| Rad Hardened | No |
| Supply Current | 120 |
| Sync/Async | Asynchronous |
| Word Size | 8(b) |
