5962-8872501LA SRAM Chip Async Dual 5V 256K-Bit 256K x 1 35ns 24-Pin CDIP
From e2v
| Access Time | 35ns |
| Address Bus | 18 b |
| Architecture | Not Required |
| Clock Freq | Not Required MHz |
| Density | 262144 Bit |
| Mounting | Through Hole |
| Number of Ports | 2 |
| Number of Words | 256K |
| Operating Supply Voltage (Max) | 5.5 V |
| Operating Supply Voltage (Min) | 4.5 V |
| Operating Supply Voltage (Typ) | 5 V |
| Operating Temp Range | -55C to 125C |
| Operating Temperature Classification | Military |
| Package Type | CDIP |
| Pin Count | 24 |
| Rad Hardened | No |
| Supply Current | 120mA |
| Sync/Async | Asynchronous |
| Word Size | 1 b |
