EPM7128ABC100-10 Electrically-Erasable Switch Matrix PLD - In-System Programming,JTAG
From Altera
| # of Cells (macros) Per Array | 16 |
| # of Product Terms Per Array | 80 |
| @Iol (A) | 4m |
| Digital Input V Max (V) | 5.7 |
| Military | N |
| Nom. Supp (V) | 3.3 |
| Number of I/O Terminals | 64 |
| Number of Input Terminals | 4 |
| Number of Output Terminals | 0 |
| Output Config | 3-State |
| Output Logic Polarity | Programmab |
| Package | BGA |
| Pins | 100 |
| Technology | CMOS |
| Total # of Logic Cell (macros) | 128 |
| Total Number of Arrays | 8 |
| Total Number of Product Terms | 640 |
| V(OL)Max.(V)Lo Level Out.Volt. | 0.45 |
| t(PHL) Maximum (S) | 10n |
| t(PLH) Maximum (S) | 10n |
