EPM5130GC100 Electrically-Erasable Switch Matrix PLD - Design security
From Altera
| # of Cells (macros) Per Array | 16 |
| # of Product Terms Per Array | 80 |
| @Iol (A) | 8m |
| Digital Input V Max (V) | 7 |
| Military | N |
| Nom. Supp (V) | 5 |
| Number of I/O Terminals | 64 |
| Number of Input Terminals | 20 |
| Output Config | Totem-Pole |
| Package | PGA |
| Pins | 100 |
| Technology | CMOS |
| Total # of Logic Cell (macros) | 128 |
| Total Number of Arrays | 8 |
| Total Number of Product Terms | 640 |
| V(OL)Max.(V)Lo Level Out.Volt. | .45 |
| t(PHL) Maximum (S) | 25n |
| t(PLH) Maximum (S) | 25n |
