{"V(OL)Max.(V)Lo Level Out.Volt.":".5","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"132","@Iol (A)":"10m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"4000","VIL Max. (TTL) (V)":".8","Package":"PGA","VIH Min. (TTL) (V)":"2","@IOH (test)":"10m","Configurable Logic Blocks":"684","Military":"N","Number of User I\/Os":"104","V(OH)Min.(V)Hi Level Out.Volt.":"2.4","Vsup (+) Maximum (V)":"7","JEDEC Std 30 Outline Code":"S-CPGA-P","Technology":"...

{"Number of Logic Blocks\/Elements":"684","Mounting":"Through Hole","Number of Usable Gates":"4000","Programmable":"Yes","Logic Cells":"684","Operating Temperature (Min)":"0C","# Registers":"568","Operating Temperature (Max)":"70C","Operating Temperature Classification":"Commercial","Package Type":"CPGA","Operating Supply Voltage (Max)":"5.5(V)","Propagation Delay Time":"4.3(ns)","Family Name":"'ACT\u2122 2'","Operating Supply Voltage (Min)":"4.5(V)","Operating Temp Range":"0C to 70C","Device System Gates":...